1. Field of the Invention
This invention relates to a driving circuit.
2. Description of the Prior Art
In driving circuits in charging pump booster circuits, two transistors connected in series between high-voltage and low-voltage both source terminals simultaneously come into a conducting state when both the transistors are push-pull operated, whereupon a leak-through current flows (see, e.g., Japanese Patent Application Laid-open No. 2000-262042, corr. to U.S. Pat. No. 6,307,407). This phenomenon is described below with reference to FIGS. 11 to 13.
As shown in FIG. 11, a bipolar transistor 100 and a bipolar transistor 101 are connected in series between a high-voltage side source terminal (VB) and a ground terminal, and also a midpoint between a resistance element 102 and a transistor 103 which are connected in series between the high-voltage side source terminal (VB) and the ground terminal is connected to a base terminal of the bipolar transistor 100. An input signal is fed to the base terminal of the bipolar transistor 100 via an inverter 104 and is also fed to a base terminal of the bipolar transistor 101 via inverters 104 and 105. By this signal, the bipolar transistor 100 and bipolar transistor 101 are push-pull operated, so that the output voltage is switched to ground potential and high-voltage side source potential (VB). In each of the inverters 104 and 105 shown in FIG. 11, a p-n junction-isolated bipolar transistor shown in FIG. 12 is used. That is, an n− silicon layer 111 is formed on an n-type silicon substrate 110, and a p+ region 112 which reaches the n− silicon substrate 110 is formed in the n− silicon layer 111 in such a way that it surrounds an element formation region. In this element formation region (p-n junction isolation island), a buried n+ layer 113 is formed. In the surface layer portion of the n− silicon layer 111 at the part of the element formation region (p-n junction isolation island), an n+ collector region 114 and a p+ base region 115 are formed standing separate from each other, and also an n+ emitter region 116 is formed in the p+ base region 115.
FIG. 13 shows waveforms on the input/output sides (α1, α2) of the inverter 104, a waveform on the output side (α3) of the inverter 105, and the ON/OFF state of the bipolar transistors 100 and 101. As shown in FIG. 13, there is a delay time τ in the bipolar transistor 100 when it is switched from ON to OFF. Hence, the moment the bipolar transistors 100 and 101 are turned ON simultaneously to come into a conducting state, a leak-through current I flows. Stated strictly, the leak-through current may inevitably flow unless at least either of the two transistors comes turned OFF. That is, where a circuit is set up which performs push-pull operation by means of two MOS transistors 120 and 121 as shown in FIG. 14, a condition may come in which as shown in FIG. 15 at least one of the two transistors 120 and 121 does not come turned OFF, at the time of which the leak-through current I flows. This leak-through current causes a trouble due to radio noise.
As a countermeasure therefor, the driving circuit disclosed in the above Japanese Patent Application Laid-open No. 2000-262042 employs a structure in which a circuit for phase control is added on the side of the base terminal of the bipolar transistor 101 shown in FIG. 11.
The addition of such a phase control circuit, however, may inevitably be a factor of enlargement of chip size.